Write-once memory (“WOM”) and one-time programmable (“OTP”) memory are terms used to categorize non-volatile semiconductor memory technologies limited to a single state change of any storage cell. Examples of such technologies include fusible link memories, electrically programmable read-only memory (“EPROM”), and electrically erasable programmable read-only memory (“EEPROM”), among others.
Storage cells of a WOM or OTP semiconductor memory array are typically initialized to the same state, whether all logical 0's or all logical 1's, during manufacturing. It is noted that examples herein assume that memory cells of an array are initialized to all logical 0's during manufacturing. However, some memory devices may be initialized to all logical 1's without any loss of generality in the foregoing disclosure.
Physical limitations associated with a WOM or OTP storage cell either prevent multiple state changes of a cell entirely or render multiple state changes difficult after having been written once following manufacturing. For example, the state of a fusible link memory cannot be changed once the fusible link has been melted with an over-current write signal because there is no way of restoring the fusible link. An EEPROM memory array may be re-programmed only by exposing the floating-gate metal oxide semiconductor field effect transistors (MOSFETs) associated with the storage cells to high-intensity ultraviolet (UV) light. The latter process uses a transparent window to facilitate access to the floating gates and involves an unwieldy erase operation using a UV light source prior to each reprogramming.
Techniques are known for “memory cell reset avoidance” (“MCRA”) encoding of data to be written to a WOM or OTP array. MCRA encoding enables multiple data word writes to a target memory location while preventing more than a single state change to any individual storage cell associated with the target memory location. Doing so is important, because writing successive data words to a target memory location would incorrectly write the data to the extent that a successive write attempts to reset one or more bits corresponding to cells of the target memory location. The state of cells already written would not be reset because of the physical limitations described above. A typical MCRA encoding technique may encode an m-bit data word D into an n-bit code word C of bit length n=(2^m)−1 bits. The code word C is then written to the target memory location rather than writing D itself. MCRA encoding thus uses additional memory cells to redundantly encode the data, with the trade-off that write-once locations in a memory array may be written to multiple times. MCRA encoding typically enables writing the target memory location T=1+2^(m−2) times. It is noted that, for purposes of this entire disclosure, “memory location,” “target memory location,” and “subset of storage cells” shall mean a set of two or more individual memory cells, each memory cell capable of storing a single code word bit. Thus, a “memory location” or “subset of storage cells” is capable of storing an entire code word.
FIG. 1 is a prior-art example MCRA coding table 100 for a data word D of length m=2. The four possible data words are listed sequentially in column 110 of the table 100. Each D to be stored is encoded in a corresponding C to be written to a memory location. C is selected from column 115 the first time the memory location is written. C is selected from column 120 the second time the memory location is written. However, the memory location is not re-written if D does not change. So, for example, if the first D to be stored is “01” 125, the memory location is written with C1=“001” 128. If at a later time a data word D=“10” 130 is to be stored at that same memory location, the memory location is re-written with C2=“101” 133. Note that the code word change from C1=“001” 128 to C2=“101” 133 does not attempt to reset any bits of the target memory location from logical “1” to logical “0” as doing so is not possible using the WOM memory types described above. However, it is also noted that the MCRA coding described attempts to write the low-order bit 135A of C1 and 135B of C2 twice, once each during the first and second writes.
Taking another example, if the first D to be stored at a memory location is “11” 140, that memory location is written with C1=“100” 144. If at a later time the data word D=“01” 125 is to be stored at that same memory location, the memory location is re-written with C2=“110” 150. Note that the code word change from C1=“100” 144 to C2=“110” 150 does not attempt to reset any bits of the target memory location from logical “1” to logical “0” as doing so is not physically possible. However, it is also noted that the MCRA coding described attempts to write the high-order bit 155A of C1 and 155B of C2 twice.